The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit device and microcomputer that are intended for fast and low-voltage operation, and to a microcomputer system based on this microcomputer.
In order for a MOS transistor to operate at a low voltage around 1 V, it must have a lower threshold voltage for the enhancement of driving ability and operation speed. However, when the threshold voltage is set too low, the MOS transistor cannot turn off completely due to its subthreshold characteristics (tailing characteristics), causing a subthreshold leakage current to flow, resulting in an increased power consumption, as described in the "1993 Symposium on VLSI Circuits Digest of Technical Papers", pp. 45-46 (May 1993).
As the sub-micron MOS transistor pattern design advances, the variation among devices of the fundamental characteristics including the threshold voltage attributable to the inequality of manufacturing process increases, as described in the "1994 Symposium on VLSI Circuits Digest of Technical Papers", pp. 13-14 (June 1994).
FIG. 15 shows the variation of threshold voltage in connection with the gate length Lg of a MOS transistor. The variation of threshold voltage due to the gate length variation increases as the gate length Lg becomes shorter.
Assuming the lower limit of threshold voltage to be 0.2 V for making the subthreshold leakage current below a certain value and the above-mentioned process causing the threshold variation to be .+-.0.15 V, the actual lower limit of threshold voltage, as the sum of these values, becomes 0.35 V.
On this account, conventional semiconductor integrated circuit devices cannot have their threshold voltage set much lower. Particularly, MOS transistors with lower power voltages operate in a state of incomplete saturation, and the operation speed of MOS transistor circuits falls sharply in response to a slight rise of the threshold voltage. Therefore, it is difficult for the conventional design methodology based on the worst-case consideration to attain the intended performance of semiconductor integrated circuit devices.